cystech electronics corp. spec. no. : c 101s3 issued date : 20 16 .0 6 . 07 revised date : 2 0 1 6 . 1 0 . 1 1 page no. : 1 / 9 mta050p01s3 cyste k product specification - 14 v p - channel enhancement mode mosfet mta050p01s 3 features ? low gate charge ? compact and low profile sot - 3 23 package ? advanced trench process technology ? high density cell design for ultra low on resistance ? pb - free lead plating pack age symbol outline ordering information device package shipping mta050p01s3 - 0 - t1 - g sot - 323 ( pb - free lead plating and halogen - free package ) 300 0 pcs / tape & reel mta050p01s 3 sot - 323 g gate s sour c e d drain g s d bv dss - 14v i d @ v gs = - 10v, t a =25 c - 1.7a r dson @v gs = - 4.5v, i d = - 1.7a 66 m (typ) r dson @v gs = - 2.5v, i d = - 1.7a 86m (typ) environment friendly grade : s for rohs compliant products, g for rohs compliant and green compound p roducts packing spec, t1 : 3000 pcs / tape & reel, 7 reel product rank, zero for no rank products product name
cystech electronics corp. spec. no. : c 101s3 issued date : 20 16 .0 6 . 07 revised date : 2 0 1 6 . 1 0 . 1 1 page no. : 2 / 9 mta050p01s3 cyste k product specification absolute maximum ratings (ta=25 ? c) parameter symbol limits unit drain - sour c e voltage v ds - 14 v gate - source voltage v gs 8 continuous drain current @ t a =25 ? c , v gs = - 4.5v (note 3) i d - 1.7 a continuous drain current @ t a =70 ? c , v gs = - 4.5v (note 3) - 1.4 pulsed drain current (notes 1, 2) i dm - 6.8 maximum power dissipation (note 3) p d 0.34 w operating junction and storage temperature range tj ; tstg - 55~+1 50 ? c thermal performance parameter symbol limit unit thermal resistance, junction - to - ambient (pcb mounted) (note 3) r ja 367 ? c /w note : 1. pulse width limited by maximum junction temper ature. 2. pulse width 300 s, duty cycle 2%. 3. surface mounted on 1 in 2 copper pad of fr - 4 board . electrical characteristics (t j =25 ? symbol min. typ. max. unit test conditions stat ic bv dss - 14 - - v v gs =0v, i d = - 25 0 a ? bv dss / ? tj - 8 - mv/ ? c reference to 25 ? c , i d = - 25 0 a v gs(th) - 0.4 - - 1.0 v v ds =v gs , i d = - 25 0 a i gss - - 10 0 n a v gs = 8 v , v ds =0v i dss - - - 1 a v ds = - 12v, v gs =0v - - - 10 v ds = - 10v, v gs =0v (tj=70 ? c ) * r ds(on) - 66 90 m ? v gs = - 4.5v, i d = - 1.7 a - 86 120 v gs = - 2.5v, i d = - 1.7 a * g fs - 5.5 - s v ds = - 5v , i d = - 2a dynamic ciss - 516 - pf v ds = - 10v, v gs =0v, f=1mhz coss - 144 - crss - 134 - t d(on) - 9.8 - ns v d s = - 1 0v, i d = - 1a, v g s = - 5 v , r g = 3.3 t r - 22.6 - t d(off) - 39.6 - t f - 21.2 - qg - 7.6 - nc v ds = - 10 v, i d = - 2 a, v gs = - 4.5 v qgs - 0.8 - qgd - 2.8 -
cystech electronics corp. spec. no. : c 101s3 issued date : 20 16 .0 6 . 07 revised date : 2 0 1 6 . 1 0 . 1 1 page no. : 3 / 9 mta050p01s3 cyste k product specification source - drain diode * v sd - - 0.9 - 1. 2 v v gs =0v, i s = - 1.7a trr - 30 - ns v gs =0v, i f = - 2 a , di f /dt=100a/ s qrr - 9.5 - nc *pulse t est : pulse width ? 300s, duty cycle ? 2% recommended soldering footprint
cystech electronics corp. spec. no. : c 101s3 issued date : 20 16 .0 6 . 07 revised date : 2 0 1 6 . 1 0 . 1 1 page no. : 4 / 9 mta050p01s3 cyste k product specification typical characteristics typical output characteristics 0 2 4 6 8 10 0 1 2 3 4 5 -v ds , drain-source voltage(v) -i d , drain current (a) -v gs =5v, 4v, 3v , 2.5v -v gs =2v -v gs =1 .5 v brekdown voltage vs ambient temperature 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature( c) -bv dss , normalized drain-source breakdown voltage i d =-250 a, v gs =0v static drain-source on-state resistance vs drain current 10 100 1000 0.01 0.1 1 10 -i d , drain current(a) r ds( on) , static drain-source on-state resistance(m) -v gs =1.5v -v gs =4.5v -v gs = 3 v -v gs = 1.8 v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0 2 4 6 8 10 -i dr , reverse drain current (a) -v sd , source-drain voltage(v) tj=25 c tj=150 c v gs =0v static drain-source on-state resistance vs gate-source voltage 40 80 120 160 200 240 280 320 360 400 0 1 2 3 4 5 -v gs , gate-source voltage(v) r ds(on) , static drain-source on- state resistance(m) i d =- 3 .6a i d =-1.7a drain-source on-state resistance vs junction tempearture 0.4 0.6 0.8 1 1.2 1.4 1.6 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature( c) r ds(on) , normalized static drain- source on-state resistance v gs =-4.5v, i d =- 1.7 a
cystech electronics corp. spec. no. : c 101s3 issued date : 20 16 .0 6 . 07 revised date : 2 0 1 6 . 1 0 . 1 1 page no. : 5 / 9 mta050p01s3 cyste k product specification typical characteristics(cont.) capacitance vs drain-to-source voltage 100 1000 0 1 2 3 4 5 6 7 8 9 10 -v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss threshold voltage vs junction tempearture 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature( c) -v gs(t h) ,normalized threshold voltage i d =-250 a i d =-1ma maximum safe operating area 0.01 0.1 1 10 0.01 0.1 1 10 100 -v ds , drain-source voltage(v) -i d , drain current (a) dc 10ms 100ms 1ms 100 s t a =25 c, tj=150 c, v gs =-4.5v, r ja =367 c/w single pulse 1 s gate charge characteristics 0 1 2 3 4 5 0 1 2 3 4 5 6 7 8 qg, total gate charge(nc) -v gs , gate-source voltage(v) v ds =-10v i d =- 2 a maximum drain current vs junctiontemperature 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 25 50 75 100 125 150 175 tj, junction temperature( c) -i d , maximum drain current(a) t a =25 c, v gs =-4.5v, r ja =367 c/w typical transfer characteristics 0 2 4 6 8 10 0 1 2 3 4 5 -v gs , gate-source voltage(v) -i d , drain current (a) -v ds =5v
cystech electronics corp. spec. no. : c 101s3 issued date : 20 16 .0 6 . 07 revised date : 2 0 1 6 . 1 0 . 1 1 page no. : 6 / 9 mta050p01s3 cyste k product specification ty pical characteristics(cont.) forward transfer admittance vs drain current 0.01 0.1 1 10 0.001 0.01 0.1 1 10 -i d , drain current(a) g fs , forward transfer adm ittance-(s) pulsed ta=25 c v ds =-5v power derating curve 0 0.1 0.2 0.3 0.4 0 20 40 60 80 100 120 140 160 t a , ambient temperature() p d , power dissipation(w) mounted on fr-4 board with minimum pad area transient thermal response curves 0.01 0.1 1 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 1.e+02 t 1 , square wave pulse duration(s) r(t), normalized transient thermal resistance single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.r ja (t)=r(t)*r ja 2.duty factor, d=t 1 /t 2 3.t jm -t a =p dm *r ja (t) 4.r ja =367 c/w
cystech electronics corp. spec. no. : c 101s3 issued date : 20 16 .0 6 . 07 revised date : 2 0 1 6 . 1 0 . 1 1 page no. : 7 / 9 mta050p01s3 cyste k product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c 101s3 issued date : 20 16 .0 6 . 07 revised date : 2 0 1 6 . 1 0 . 1 1 page no. : 8 / 9 mta050p01s3 cyste k product specification recommended wave soldering condition product peak temperature so ldering time pb - free devices 260 +0/ - 5 ? c 5 +1/ - 1 seconds recommended temperature profile for ir reflow profile feature sn - pb eutectic assembly pb - free assembly average ramp - up rate (tsmax to tp) 3 ? c /second max. 3 ? c /second max. preheat ? tempera ture min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 ? c 150 ? c 60 - 120 seconds 150 ? c 200 ? c 60 - 180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 ? c 60 - 150 seconds 217 ? c 60 - 150 seconds peak temperature(t p ) 240 +0/ - 5 ? c 260 +0/ - 5 ? c time within 5 ? c of actual peak temperature(tp) 10 - 30 seconds 20 - 40 seconds ramp down rate 6 ? c /second max. 6 ? c /second max. time 25 ? c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of the packag e, measured on the package body surface.
cystech electronics corp. spec. no. : c 101s3 issued date : 20 16 .0 6 . 07 revised date : 2 0 1 6 . 1 0 . 1 1 page no. : 9 / 9 mta050p01s3 cyste k product specification sot - 3 23 dimension dim millimeters inches dim millimeters inches min. max. min. max. min. max. min. max. a 0. 900 1.100 0. 035 0.043 e 1 2.150 2.450 0.085 0.096 a1 0.000 0. 1 00 0.00 0 0. 004 e 0.650 typ 0.026 typ a2 0. 900 1.000 0. 035 0. 039 e1 1.200 1.400 0. 047 0. 055 b 0. 200 0. 4 00 0. 008 0. 016 l 0. 525 ref 0. 021 ref c 0.0 80 0. 150 0.003 0.006 l1 0. 260 0.460 0. 010 0.018 d 2.000 2.200 0.079 0.087 ? 0 8 0 8 e 1.150 1.350 0.045 0.053 note s: 1 . controlling dimension: millimeters. 2 . maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please contact your local cyste k sales office. material: ? lead: pure tin pla ted. ? mold compound: epoxy resin family, flammability solid burning class: ul94v - 0 . important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the pr ior written approval of cyste k . ? cyste k reserves the right to make changes to its products without notice. ? cyste k semiconductor products are not warranted to be suitable for use in life - support applications, or systems. ? cyste k assumes no liability for any consequence of customer product design, infringement of patents, or application assistance. style: pin 1. gat e 2. source 3. drain 3 - lead sot - 323 plastic surface mounted package cyste k package code: s3 marking: a5p date code te
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